Principal Engineer - PCIe RTL Design

1w1 week ago

Marvell

Bengaluru, IN · Full-time · INR 6,000,000 – INR 9,000,000

About this role

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, innovative technology enables new possibilities. At Marvell, affect the arc of individual lives and lift the trajectory of entire industries.

Own and drive PCIe/CXL subsystem micro architecture definition, RTL implementation, and integration into high-performance silicon platforms. Collaborate closely with architecture teams to translate requirements into robust RTL designs. Partner across design verification, physical design, DFT, and silicon bring-up teams for end-to-end execution.

Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU develops leading-edge data processing silicon for carrier, cloud/enterprise, and automotive compute. Focus on custom ASIC business, cloud AI solutions, enterprise/carrier solutions including the CXL product line. Power next-generation workload acceleration platforms through technical innovations.

Drive design quality improvements, coding best practices, and reuse across projects. Participate in design reviews, milestone reviews, and cross-functional technical discussions. Mentor junior designers and provide technical leadership within the PCIe/CXL design domain.

Requirements

Master’s/Bachelor’s degree in Electronics/Electrical Engineering with 18+ years of relevant experience in RTL design
Experience on end-to-end PCIe/CXL subsystem RTL design execution and sign-off
Proven experience delivering complex PCIe/CXL IP or subsystems from architecture through RTL closure
Strong hands-on experience in SystemVerilog / Verilog RTL development
Expertise in PCIe protocol architecture including link, transaction, and PHY interaction layers
Strong understanding of CXL.io, CXL.cache, and CXL.mem architectures
Deep knowledge of ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE)
Experience designing high-performance, low-latency data paths and handling ordering, coherency, and error mechanisms

Responsibilities

Own and drive PCIe/CXL subsystem micro architecture definition, RTL implementation, and integration
Collaborate closely with Architecture teams to translate requirements into robust RTL designs
Work with Design Verification teams on test-plan reviews, debug, and coverage closure
Partner with Physical Design and DFT teams to ensure PD-friendly and DFT-ready RTL
Support silicon bring-up and post-silicon debug, working with firmware and validation teams
Drive design quality improvements, coding best practices, and reuse across projects
Participate in design reviews, milestone reviews, and cross-functional technical discussions
Mentor junior designers and provide technical leadership within the PCIe/CXL design domain

Benefits

Workstyle within an environment of shared collaboration, transparency, and inclusivity
Tools and resources to succeed in doing work that matters
Opportunities to grow and develop with the company